ATPG was developed to explicitly test each gate and path in an integrated circuit (“IC”) design. As ICs have become larger and more complex, the amount of logic to be tested per input/output test pin has increased dramatically.
Test Compression is a technique used as part of a Design For Test (“DFT”) method to reduce the time and cost of testing integrated circuits. Straightforward application of scan techniques can result in large vector sets with corresponding long tester time and memory requirements. Test Compression takes advantage of the small number of significant values (care bits) techniques to reduce test data and test time, by decompressing the scan input on chip and compressing the test output. This technique allows highly compressed test stimuli to be applied from low-pin count testers and compressed test responses to be measured.
Test mode power is one of many important test quality metrics considered during ATPG. For example, poorly managed power dissipation during test mode can (i) impact design performance and quality-of-test and (ii) may lead to IR drop issues and false failures on a tester. Scan-based manufacturing tests of low power designs often exceed the very tight functional constraints on average and instantaneous logic switching. For example, the logic activity during the shift and launch-capture of test pattern data may lead to excessive power dissipation and voltage droop. Specifically, a scan flop can be at a first value (e.g., “0” or “1”) during the scan load but can capture another value (e.g., “1” or “0”) during the capture cycle (i.e., once the functional clock is applied after scan shift). The captured values are generally dependent on the scan load values as well as the associated functional logic. Further, the captured values can be more random in 0/1 distribution than the scan load pattern. As such, reducing the switching activity between the shift and launch-capture of the test pattern data can contribute to reducing some of the power dissipation during ATPG as well.
Current solutions directed to reducing the switching activity and, therefore, achieving certain test power targets, are usually applied after ATPG generates the test patterns. Clock gating, for example, is commonly utilized to reduce functional power dissipation in the integrated circuit design. With clock gating, functional clocks are temporarily gated from reaching areas of the integrated circuit chip that are not required for functional operation at that time. Specifically, care bits required to temporarily gate the specific functional clocks (i.e., corresponding to flops that do not require functional operation) are merged with an already generated test pattern. In other words, the generated test patterns are “post-processed” with the merging care bits. However, “post-processing” presents other problems. For example, it is possible that certain “merging” care bits will be prevented from being post-processed into the generated test patterns because of conflicts with existing care bits (e.g., for fault detection) in the generated test pattern. As such, with an increase in the number of conflicts with existing care bits, the likelihood of achieving desired power targets for specific test patterns will decrease.
Furthermore, with regard to compressed test patterns, in order to better manage power dissipation during ATPG, it is also important to consider the physical locations of the scan channels in relation to the integrated circuit. Specifically, since test compression techniques result in a greater number of scan channels, the physical proximity of the scan channels might result in regions of increased thermal activity, e.g., “hot spots.”
As such, there is a need for physically-aware systems and methods for optimizing the power dissipated during ATPG.